1. Field of the Invention
The present invention generally relates to the field of metal-oxide-semiconductor (MOS) transistors, and more particularly, to a method for forming a MOS transistor comprising strained silicon.
2. Description of the Prior Art
A metal-oxide-semiconductor is a common electronic device used in integrated circuits. The MOS transistor is a semiconductor device usually formed by a gate, a source, and a drain. By utilizing channel effects generated by the gate of the MOS under a plurality of different gate voltages, the MOS is often made to function as a digitalized solid switch being applied on various integrated circuits for memory or logic devices.
Please refer to FIGS. 1-3, where FIGS. 1-3 are schematic diagrams illustrating a conventional method of fabricating a MOS transistor. As shown in FIG. 1, a semiconductor substrate 16 is first prepared. A gate dielectric layer 14 and a gate 12, which is positioned on the dielectric layer 14, are formed on the semiconductor substrate 16, where the gate dielectric layer 14 and the gate 12 form a gate structure. Subsequently, a shallow source extension 17 and a shallow drain extension 19 are formed within the semiconductor substrate 16 on two opposite sides of the gate structure 12. The shallow source extension 17 and the shallow drain extension 19 are separated by a channel region 22 of the MOS transistor. For an N-type metal-oxide-semiconductor (NMOS) transistor, the dopant species of the shallow source extension 17 and the shallow drain extension 19 may be N-type dopant species, such as arsenic, antimony, or phosphorous. Next, a liner 30 and a spacer 32 are formed around the sidewalls of the gate 12.
As shown in FIG. 2, an ion implantation process is carried out afterwards to implant dopants into the semiconductor substrate 16. Accordingly, a source region 18 and a drain region 20 are formed on the opposite sides of the gate 12 within the semiconductor substrate 16, thereby forming a MOS transistor 34. As mentioned above, the dopant species may be N-type dopant species, such as arsenic, antimony, or phosphorous, for the NMOS transistor.
Furthermore, as shown in FIG. 3, a stressed cap layer 46 is formed above the semiconductor substrate 16 and to cover the surface of the MOS transistor 34. The stressed cap layer 46 comprises mainly of silicon nitride so as to provide a tensile stress on the MOS transistor 34. Next, an activating process is performed on the stressed cap layer 46 to make the MOS transistor 34 memorizes or retains the stress.
As known to those skilled in the art, the higher the stress of the stressed cap layer 46 is, the more the stress of the stressed cap layer 46 can effectively expand the lattice arrangement in the channel region 22 of the semiconductor substrate 16. Accordingly, the Ion gain of the MOS transistor 34 should be increased as well. However, the stress of the stressed cap layer 46 may crack or break either the stressed cap layer 46 itself or the structure of the MOS transistor 34 when the stress of the stressed cap layer 46 has reached beyond a limit. Thereafter, the functionality of the stressed cap layer 46 is dramatically reduced, and the operation of the MOS transistor 34 is thereby damaged.